1. Field of the Invention
The invention relates in general to a multi-chip package with leadframe, and more particularly to a multi-chip package whose two chips are separately mounted on at least two die pads at different altitudes.
2. Description of the Related Art
Conventionally, an encapsulant is applied in covering several chips in multi-chip package in order to enhance capacity and function in a package. For example, a multi-chip package is provided by combining and packing two chips having the same or similar sizes. The two chips include the same function or two different functions.
Referring to FIG. 1, it is a cross-sectional view of a conventional multi-chip package. A multi-chip package 10 includes a leadframe 111, two chips 102, 104 having the same size or similar sizes, a dummy chip or a spacer 105, a number of wires 114, 116 and an encapsulant 118. The leadframe 111 has a die pad 106 and a number of inner leads 112. The die pad 106 has a chip attaching surface 106a and an unoccupied surface 106b opposite to the chip attaching surface 106a. Each of the inner leads 112 has a wire connecting surface 112a and a wire non-connecting surface 112b opposite to the wire connecting surface 112a. The chip 102 has an active surface 102a and an inactive surface 102b opposite to the active surface 102a. The peripheral region of the active surface 102a has a number of bond pads 1021. The chip 104 has larger size than the chip 102. The chip 104 has an active surface 104a and an inactive surface 104b opposite to the active surface 104a. The peripheral region of the active surface 104a has a number of bond pads 1041. The inactive surface 104b is attached to the chip attaching surface 106a via an adhesive layer 110, so that the chip 104 is disposed on the die pad 106.
The spacer 105 has smaller size than the chips 102 and 104. The spacer 105 includes an upper surface 105a and a bottom surface 105b opposite to the upper surface 105a. The bottom surface 105b is attached to the central region of the active surface 104a via an adhesive layer 109, so that the spacer 105 is disposed on the chip 104. Part of the inactive surface 102b is attached to the upper surface 105a via an adhesive layer 108, so that the chip 102 is disposed on the spacer 105. The wires 114 are used for electrically connecting the bond pads 1021 to the wire connecting surfaces 112a. The spacer 105 is used for providing a distance between the chips 102 and 104 to avoid the chip 102 pressing the wires 116. The wires 116 are used for electrically connecting the bond pads 1041 to the wire connecting surfaces 112a. The encapsulant 118 is used for covering the die pad 106, the chips 102, 104, the bond pads 1021, 1041, the wires 114, 116 and part of the inner leads 112.
A spacer or a dummy chip is inserted between the two chips with the same size or similar sizes in order to provide a distance between the two chips to avoid the upper chip pressing the wire electrically connected the bottom chip. However, it has to be considered the required thickness and the material costs for the design of inserting the spacer or dummy chip in the multi-chip package. Also, much materials with different coefficient of thermal expansion (CTE), such as the die pad, the spacer or the dummy chip, the two chips, part of the inner leads and the encapsulant, assembled in the multi-chip package will cause the more serious mismatch of coefficient of thermal expansion (CTE) of the multi-chip package and has great effect on the reliability of the multi-chip package.